50.002 CS
50.002 1D & 2D Project
Duration: Week 1-12
In this project, you are to design and create an Electronic Hardware Prototype using an FPGA in a group of 5-7 pax.
Language: We will provide resources about programming in the hardware design language (HDL) called Lucid. However, you are free to use Verilog if you’re confident, but we will not be able to provide a lot of support for that. Lucid is much simpler than Verilog, it is more than capable to get the job done for this project, hence we chose this as our teaching material.
IDE: Alchitry Labs
Hardware: Alchitry Au (Artix 7 FPGA). This is given in your 1D Kit along with other useful stuffs
Tool (to convert HDL to binary, build your project): Vivado
Each group’s contact person will need to collect your group’s 1D Kit (containing Alchitry Au FPGA). Refer to your course handout for futher details.
Assessment weightage & Rubric
- Checkoff 1: ALU 3% (Week 8)
- Checkoff 2: Datapath 5% (Week 9)
- Checkoff 3: Live Demo & Exhibition 12% (Week 12)
- Checkoff 4: Report + Poster + Video 2% (Week 12)
- Checkoff 5: Peer Review 8% (Week 13)
- Optimisation 4% (Week 12)
- Sustainability & Inclusivity 2% (Week 12)