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50.002 CS
Home
Roadmap
Hardware Related Topics
Basics of Information
Digital Abstraction
CMOS Technology
Logic Synthesis
Sequential Logic
Sequential Timing Animation
Finite State Machine
Turing Machine and Programmability
Designing an Instruction Set
Building Beta CPU
Software Related Topics
Beta CPU Diagnostics
Assemblers and Compilers
Stack and Procedures
Memory Hierarchy
Cache Design Issues
Virtual Memory
Virtual Machine
Asynchronous Handling of IO Devices
Problem Set
Basics of Information
Digital Abstraction
CMOS Technology
Logic Synthesis
Sequential Logic
Finite State Machine
Turing Machine
Designing an Instruction Set
Beta CPU Datapath
Beta Diagnostics
Assemblers and Compilers
Stack and Procedures
The Memory Hierarchy
Cache Design Issues
Virtual Memory
Asynchronous I/O Handling
Labs
Lab 0 - Digital Abstraction
Lab 1 - CMOS
Lab 2 - Combinational and Sequential Logic with FPGA
Lab 3 - Arithmetic Logic Unit with FPGA
Lab 4 - Beta Processor with FPGA
Lab 4 - Beta Processor with FPGA (Advanced)
Lab 5 - Assembly Language
1D&2D Project (FPGA)
Installation Guide
Lucid V1 (Legacy)
FPGA Tutorial for Babies
FPGA Tutorial for Toddlers
FPGA Tutorial for Children
Debugging for the Frantic
Lucid V2
Running Vivado on Apple Silicon mac
Documentation
Useful Resources
Contribute to this site on GitHub
eDimension
1D&2D Project (FPGA)
Lucid V1 (Legacy)
Lucid V1
Lucid V1 was used in 50.002 prior to 2025. The official tutorial can be found
here
.
50.002 CS