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50.002 CS
Home
Hardware Related Topics
Basics of Information
Digital Abstraction
CMOS Technology
Logic Synthesis
Sequential Logic
Sequential Timing Animation
Finite State Machine
Turing Machine and Programmability
Designing an Instruction Set
Building Beta CPU
Software Related Topics
Beta CPU Diagnostics
Assemblers and Compilers
Stack and Procedures
Memory Hierarchy
Cache Design Issues
Virtual Memory
Virtual Machine
Asynchronous Handling of IO Devices
Labs
Lab 1 - Digital Abstraction
Lab 2 - Combinational Logic
Lab 3 - Clocked Circuits
Lab 4 - Control Sequencing
Lab 5 - Arithmetic Logic Unit (ALU)
Lab 6 - Beta Processor
Supplementary
Digital Abstraction (JSIM)
CMOS (JSIM)
Beta Processor IO
Assembly Language
Verilog
Lab 1 - Digital Abstraction
Lab 2 - Combinational Logic
Lab 3 - Clocked Circuits
Lab 4 - Control Sequencing
Lab 5 - Arithmetic Logic Unit (ALU)
Lab 6 - Beta CPU
Sensitivity List
Nuances in Verilog
Problem Set
Basics of Information
Digital Abstraction
CMOS Technology
Logic Synthesis
Sequential Logic
Finite State Machine
Turing Machine
Designing an Instruction Set
Beta CPU Datapath
Beta Diagnostics
Assemblers and Compilers
Stack and Procedures
The Memory Hierarchy
Cache Design Issues
Virtual Memory
Asynchronous I/O Handling
1D&2D Project (Details)
50.002 1D Project
Checkoff 1 (ALU)
Checkoff 2 (Datapath)
Checkoff 3 (Live Demo)
Checkoff 4 (Writeup, Poster, Video, and Report)
Checkoff 5 (Peer Review)
50.002 Sample Project
50.002 2D Project
Data Structure and Hardware Optimisation
Enhanced Game Features
UI/UX Enhancement
Sustainability
1D&2D Project (FPGA)
Installation Guide
Running Vivado on Apple Silicon mac
Using Vivado + Verilog with Alchitry Au
Lucid V1 (Legacy)
FPGA Tutorial for Babies
FPGA Tutorial for Toddlers
FPGA Tutorial for Children
Debugging for the Frantic
Lucid V2
Alchitry Pinout
Board Reset
Random Number Generation
Seven Segment
LucidV2 Pitfalls
WS2812B
MAX7219
RGB LED Matrix (HUB 75)
SN74HC595
Debugging Strategies
Testbench
Clocks
Documentation
CSChatbot
Roadmap
Useful Resources
Contribute to this site on GitHub
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50.002 CS